Integrated circuits (ICs) may include billions of transistors designed as logic circuitries which perform specific functions. After manufacturing, functionality of the ICs are tested using for example, IC testers. A failure event triggers a failure analysis flow to identify causation of the failure. For example, the failure analysis flow debugs the failures.
An important aspect of debugging is defect localization, such as hot spots. However, conventional IC testers generate large amount of artifacts (false hot spots) along with the hot spots. The large number of artifacts increases the amount of time for debugging the failure. This negatively impacts product yield ramp, decreasing profit margin.
From the foregoing discussion, it is desirable to improve defect localization.